پروطه وریلاگ ساخت cpu اسان با برنامه زایلینکس
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A Processor with Von Neumann
Memory in Two Modes
In this document, we describe a processor with two modes: mode 1 and mode 0. This
processor uses Von Neumann memory architecture in both modes, where both data and
instructions are stored in the same memory space.
1. Single Memory Storage: Both program instructions and data share the same memory
resources.
2. Limitations: memory access is a bottleneck for performance.
Mod 1:
The table below illustrates the opcode instructions used in this processor.
Opcode Description Example
Instruction Example Result
0000
Add two registers and
save the result in the
0000 0001 0010 R[1] ← R[1] + R[2]
1st reg
0001
Subtract two registers
and save the result in
the 1st reg
0001 0001 0010 R[1] ← R[1] − R[2]
Multiply two registers
and save the 8 least
significant bits of
0010
0010 0011 0100 result in R[1], and the
R[2] ← (R[3] ∗ R[4])[15 : 8]
R[1] ← (R[3] ∗ R[4])[7 : 0]
8 most significant bits
in R[2]
0011
And two registers and
save the result in the
1st reg
0011 0001 0010 R[1] ← R[1]&R[2]Or two registers and
0100
save the result in the
0100 0001 0010 R[1] ← R[1] | R[2]
1st reg
0101
Xor two registers and
save the result in the
1st reg
0101 0001 0010 R[1] ← R[1]ˆR[2]
Move the value of the
0110
2nd register to the
first reg
0110 0001 0010 R[1] ← R[1]
0111
Move the value of the
2nd operand to the
first register
0111 0001 1110 R[1] ← 14
1000
Shift the first register
left as much the value
1000 0001 0010 R[1] ← R[1] << R[2]
of the 2nd register
1001
1001 0001 0010 1010 Load from memory 1010 00010000 R[0] ← Mem[16]
1011 Shift the first register
right as much the
value of the 2nd
register
1011 00010000 R[1] ← R[1] >> R[2]
Save to memory Mem[16] ← R[0]
On the rising edge of the clock, an instruction is sent from memory to the CPU.
The CPU receives these instructions on the falling edge of the clock and executes the
operations.
Some operations require sending data back to the memory.
To achieve this, it needs to activate an Enable signal connected to the memory during the
same clock edge, allowing the data to be sent to memory.
The memory will receive the data when this Enable = 1.
Now, how do we determine where to store the data?
Before the STORE instruction is sent from memory to the CPU, the address is already
included in the instruction.
Thus, the CPU must keep this address beforehand to store the data at the correct location
during the return path.
The primary challenge in this mode is ensuring proper synchronization between the
components.
In the CPU, there are 16 registers, each 8 bits wide. Why are they 8-bit?
Refer to the last two instructions, which involve memory operations.
Since both instructions and data are stored in the same memory, the memory size must
align with the length of the instructions, which is 12 bits.But this raises a question: when sending 8-bit data to memory, what happens to the
remaining 4 bits?
The solution to this problem is simple. Think about it carefully. These kinds of challenges
are common in projects and require attention to detail.
Memory Size:
The total memory size is flexible, but it must meet the following conditions:
1. 2. 3. It must be a power of 2.
Avoid making it excessively large to prevent unnecessary complexity.
A size like 64 seems reasonable and manageable.
Simplification for Testing:
To make testing easier, include the following code in your memory module:
𝒊𝒏𝒊𝒕𝒊𝒂𝒍 $𝒓𝒆𝒂𝒅𝒎𝒆𝒎𝒃("𝒓𝒂𝒎𝒔
𝟐𝟎𝒄. 𝒅𝒂𝒕𝒂"
_
, 𝒎𝒆𝒎𝒐𝒓𝒚, 𝟔𝟑, 𝟎);
You also need to create a file in your project folder with the extension .data.
For example, name the file rams_20c.data.
The range 63, 0 in the code depends on your memory definition.
In this .data file, you can input 12-bit instructions, each on a new line.
For example, here’s a Fibonacci sequence program that calculates the value 8:
Fibonacci Program (12-bit Instructions for .data File):
011100010001
011000100001
000000010010
000000100001
000000010010
000000100001
011000000010
101100010000Module Setup:
You need a main module that connects your CPU and memory.
The inputs to this module are clock and mode.
In your testbench, initialize the clock and set the mode appropriately:
1. Start the clock.
2. Set the mode to 1.
Steps for Testing:
1. 2. 3. Copy the above instructions into the rams_20c.data file.
Simulate the code using your testbench.
Ensure you set the mode to 1 during the simulation.
Mod 0:
One of the challenges in computer science is balancing between complex processing
with short instructions and simple processing with longer instructions. Mode 0
specifically addresses this concept. Here, we work with simpler instructions, but they
require more effort because they are very basic.
In this mode, memory contains two types of data:
1. 2. Instructions, which start with 0.
Data, which start with 1.
Key Characteristics of Mode 0:
1. Energy Efficiency:
To reduce CPU energy consumption, only three registers are used: Register 1,
Register 2, and Register 3.
2. Supported Instructions:
o Addition: Performed using Registers 1 and 2; the result is stored in Register 3.
o Subtraction: Similar to addition, but performs subtraction instead.
o Jump: Two types are supported: upward jump and downward jump,
depending on how you define memory in your test file.
o Memory Writing: Data can be written to memory only from Register 3 or
Register 2, each with a distinct instruction.3. Memory Data Handling:
If the memory points to a data value, it sends that data directly to the CPU. (into
Register 1 or Register 2) based on the second most significant bit of the data.
Example Instructions
Instruction
Type Operation Addition Add values from
Registers 1 and 2 0
000
_
_
XXXXXXXX Subtraction
Example Used Subtract value in
Register 1 from
Register 2
Notes
R[3] ←R[1]+R[2]
0
001
_
_
XXXXXXXX R[3] ←R[2]-R[1]
Write value from
Write to
Register 2 to
0
010
00010100 _
_
Memory R2
Write value of R2 to addres 20
depend on test file.
memory
Write to
Memory R3
Write value from
Register 3 to
memory
0
011
00010101 _
_
Write value of R3 to addres 21
depend on test file.
I ( as pointer in momry) to I
Jump
(Downward)
Jump to a later
instruction 0
100
_
_
00010100
Downward with value 20
depend on test file.
Jump
(Upward)
Jump to an earlier
instruction 0
101
_
_
00010100
I ( as pointer in momry) to I
Upward with value 20 depend
on test file.
Load data from
Load Data R1
memory to Register
1
0
_
_
0000000001 R[1] ←1
1
Load Data R2
Load data from
memory to Register
2
1
1
_
_
0000000001 R[2] ←1
You need to implement Mode 1 first, and writing Mode 0 won't be difficult afterward.
The main point is that you should be able to switch the mode without altering the
structure, the number of input and output bits in memory, and the CPU (including the
memory and CPU registers).
In short, you should change the test file and set the mode to 0 in the testbench. The code
must still be able to run the simulation successfully.Fibonacci Program (12-bit Instructions for .data File in
mode 0):
010000010100
000000000000
001000010100
001100010101
010000010011
000100000000
001100011000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
100000000001
110000000001
010100010101
100000000001
110000000100
010100010100Bonuses:
1. Parameterize Data Sizes:
Ensure that the size of instructions, data, and registers can be handled using
parameters. The initial values of these parameters should be based on the
documentation.
2. Sum and Average in Two Modes:
Implement functionality to sum 8 numbers together and calculate their average in
both modes.
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