پروژه وریلاگ ساخت cash اسان با برنامه

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In this project you will design and implement a two-level cache hierarchy in Verilog, consisting of a direct-mapped L1 cache and a 2-way set-associative L2 cache. The objective is to model cache behavior, associativity, replacement policy, and access latency as studied in the Computer Architecture course. Only tags, valid bits, and replacement metadata are modeled. No actual cache data payload or memory array is required.

Controller: A centralized FSM is required to control cache access, handle latency counters, manage promotion/demotion, and generate the done signal. Cache Architecture • L1 Cache: o Direct-mapped (1-way) o Fastest access o Tag + valid bit per line • L2 Cache: o 2-way set associative o Slower than L1 o Each set contains two tags, two valid bits, and one LRU bit • Memory o No data storage o Modeled only via latency

Assumptions • Non-inclusive caches: L1 and L2 may contain same blocks (duplication). • Block size (line of data): abstracted away (we only use address tag bits). • No actual memory array is modeled – memory contents do not matter for this simulation. • Single outstanding request at a time (no pipeline, just one instruction at a time) • Write-through, no-write-allocate • Overwriting during promotion/demotion allowed

Policies • Read Policy o L1 hit: complete after L1 latency (no need to change anything) o L2 hit: promote to L1, demote L1 victim to L2 (overwriting occurs). o Miss: fetch from memory, install into L1, demote L1 victim (overwriting occurs). • Write Policy o Write hit (both L1 & L2): invalidate the hit cache line (no new allocation). o Write miss: No-write-allocate on write miss (writes go to memory). • Reset Behavior o On reset, all valid and LRU bits must be cleared and the FSM returned to IDLE. Note: No need for actual memory interactions. In read-miss replace L1 victim with the new data (fetched from address) and demote L1 victim to L2 (L1 victim is written to L2 only if it’s valid), and in write-hit just invalidate the hit cache lines. Note: hit happens when valid bit is 1 and tag matches address tag segment. Note: for L2 being a 2-way cache you need to consider L2-hit as the result of hit of each “way”. Assume this as the L2-hit: L2-hit = L2-way0-hit OR L2-way1-hit. Note: LRU-bit is updated on every L2 access. Note: demotion happens in way0 or way1 based on LRU-bit. Note: be careful with the promoting and demoting actions, because L1 and L2 have different index widths, replacing cannot be done by copying tags. You must reconstruct the block’s full-block-address; one part of your assignment is to correctly promote & demote blocks.

Timing & Latency Modeling • L1 latency: 1 cycle • L2 latency: 5 cycles • Memory latency: 20 cycles The right sequence of actions must be considered; The controller must first check L1, then only if L1 misses check L2, then perform install/promote/demote/invalidate operations. Tag & Index Layout • L1 index (set): address[6:4] • L2 index (set): address[7:4] • L1 tag: address[31:7] • L2 tag: address[31:8] Testbench Requirements Your tb must run multiple scenarios and show waveforms confirming valid/hit behavior. Must include tests for: 1. Read hit (L1). 2. Read hit (L2). 3. Read miss. 4. Write hit (L1). 5. Write hit (L2). 6. Write miss. Note: include any necessary bit(s) for inspection to support successful completion.

Deliverables Submit a zip file containing: • Verilog sources • Testbench • Document (report) explaining FSM, code and cache logic Note: include any assumptions you made (besides the ones stated in the project documentation) in your report. Submission Instructions • Name the zip: CA_Project__.zip • Upload to Quera before deadline. • Do not hesitate to ask any questions.

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